Tegra: memctrl_v2: platform handler for TZDRAM setup

The Tegra memctrl driver sets up the TZDRAM fence during boot and
system suspend exit. This patch provides individual platforms with
handlers to perform custom steps during TZDRAM setup.

Change-Id: Iee094d6ca189c6dd24f1147003c33c99ff3a953b
Signed-off-by: Steven Kao <[email protected]>

diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
index 0567aa9aff5cc0da61508e7675d200cd5f32d3dd..15314e7228e01de25bbb5d9a27483d1624546eb7 100644 (file)
--- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
+++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
@@ -30,6 +30,7 @@ static uint64_t video_mem_size_mb;
  * provide typical implementations that will be overridden by a SoC.
  */
 #pragma weak plat_memctrl_tzdram_setup
+
 void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes)
 {
        ; /* do nothing */
@@ -154,26 +155,10 @@ void tegra_memctrl_restore_settings(void)
  */
 void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes)
 {
-       /*
-        * Setup the Memory controller to allow only secure accesses to
-        * the TZDRAM carveout
-        */
-       INFO("Configuring TrustZone DRAM Memory Carveout\n");
-
-       tegra_mc_write_32(MC_SECURITY_CFG0_0, (uint32_t)phys_base);
-       tegra_mc_write_32(MC_SECURITY_CFG3_0, (uint32_t)(phys_base >> 32));
-       tegra_mc_write_32(MC_SECURITY_CFG1_0, size_in_bytes >> 20);
-
        /*
         * Perform platform specific steps.
         */
        plat_memctrl_tzdram_setup(phys_base, size_in_bytes);
-
-       /*
-        * MCE propagates the security configuration values across the
-        * CCPLEX.
-        */
-       mce_update_gsc_tzdram();
 }
 
 /*

diff --git a/plat/nvidia/tegra/soc/t186/plat_memctrl.c b/plat/nvidia/tegra/soc/t186/plat_memctrl.c
index 71904a8f6f348a17ace0a4de25f74e4abaaf2535..376ee86df9bda7bccf535e905c33bcc9a808918b 100644 (file)
--- a/plat/nvidia/tegra/soc/t186/plat_memctrl.c
+++ b/plat/nvidia/tegra/soc/t186/plat_memctrl.c
@@ -7,6 +7,7 @@
 #include <assert.h>
 #include <common/bl_common.h>
 
+#include <mce.h>
 #include <memctrl_v2.h>
 #include <tegra_mc_def.h>
 #include <tegra_platform.h>
@@ -546,8 +547,15 @@ void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes)
 {
        uint32_t val;
 
-       (void)phys_base;
-       (void)size_in_bytes;
+       /*
+        * Setup the Memory controller to allow only secure accesses to
+        * the TZDRAM carveout
+        */
+       INFO("Configuring TrustZone DRAM Memory Carveout\n");
+
+       tegra_mc_write_32(MC_SECURITY_CFG0_0, (uint32_t)phys_base);
+       tegra_mc_write_32(MC_SECURITY_CFG3_0, (uint32_t)(phys_base >> 32));
+       tegra_mc_write_32(MC_SECURITY_CFG1_0, size_in_bytes >> 20);
 
        /*
         * When TZ encryption is enabled, we need to setup TZDRAM
@@ -565,4 +573,10 @@ void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes)
 
        val = tegra_mc_read_32(MC_SECURITY_CFG3_0) & MC_SECURITY_BOM_HI_MASK;
        mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_TZDRAM_ADDR_HI, val);
+
+       /*
+        * MCE propagates the security configuration values across the
+        * CCPLEX.
+        */
+       (void)mce_update_gsc_tzdram();
 }